From bc28fd7cabdb21c308815654efd7d6e6593bbcaf Mon Sep 17 00:00:00 2001 From: Babu Moger Date: Mon, 7 Oct 2019 15:48:39 -0500 Subject: [PATCH 1865/2944] x86/cpufeatures: Add feature bit RDPRU on AMD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix #29429936 commit 9d40b85bb46a99bc95dad3a07787da93b0a018e9 upstream AMD Zen 2 introduces a new RDPRU instruction which is used to give access to some processor registers that are typically only accessible when the privilege level is zero. ECX is used as the implicit register to specify which register to read. RDPRU places the specified register’s value into EDX:EAX. For example, the RDPRU instruction can be used to read MPERF and APERF at CPL > 0. Add the feature bit so it is visible in /proc/cpuinfo. Details are available in the AMD64 Architecture Programmer’s Manual: https://www.amd.com/system/files/TechDocs/24594.pdf Signed-off-by: Babu Moger Signed-off-by: Borislav Petkov Cc: Aaron Lewis Cc: ak@linux.intel.com Cc: Fenghua Yu Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Josh Poimboeuf Cc: "Peter Zijlstra (Intel)" Cc: robert.hu@linux.intel.com Cc: Thomas Gleixner Cc: Thomas Hellstrom Cc: x86-ml Link: https://lkml.kernel.org/r/20191007204839.5727.10803.stgit@localhost.localdomain Signed-off-by: Artie Ding Acked-by: Caspar Zhang --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 1875713..30e506c 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -291,6 +291,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ -- 1.8.3.1