From a28ee43468b4f7382b2867e2dd35689f37a18f1f Mon Sep 17 00:00:00 2001 From: Srinivas Pandruvada Date: Tue, 19 Nov 2019 16:22:54 -0800 Subject: [PATCH 1928/2944] tools/power/x86/intel-speed-select: Display TRL buckets for just base config level task #29499913 commit 1434a3d357d656d4b11fcbdc9b6c35dc673292a0 upstream When only base config level is present, this tool is displaying TRL (Turbo-ratio-limits) by reading legacy MSR. In this case, also present core count for TRL by reading MSR 0x1AE. Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko Signed-off-by: Erwei Deng Reviewed-by: Artie Ding --- tools/power/x86/intel-speed-select/isst-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/power/x86/intel-speed-select/isst-core.c b/tools/power/x86/intel-speed-select/isst-core.c index aa19c99..d14c7bc 100644 --- a/tools/power/x86/intel-speed-select/isst-core.c +++ b/tools/power/x86/intel-speed-select/isst-core.c @@ -681,6 +681,7 @@ int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev) } isst_get_get_trl_from_msr(cpu, ctdp_level->trl_sse_active_cores); + isst_get_trl_bucket_info(cpu, &ctdp_level->buckets_info); continue; } -- 1.8.3.1