From 32b4c3210d3de5a836ad9651b5053c64e3dc9cd4 Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Thu, 22 Oct 2020 10:23:08 +0800 Subject: [PATCH 2196/2944] Intel: perf/x86/intel: Move BTS index to 47 to #31064126 commit d39fcc32893dac2d02900d99c38276a00cc54d60 upstream Backport summary: backport to kernel 4.19.57 for ICX perf topdown support The bit 48 in the PERF_GLOBAL_STATUS is used to indicate the overflow status of the PERF_METRICS counters. Move the BTS index to the bit 47. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20200723171117.9918-5-kan.liang@linux.intel.com Signed-off-by: Yunying Sun Signed-off-by: Peng Wang Reviewed-by: Artie Ding --- arch/x86/include/asm/perf_event.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index a3a2bef..7cb76f8 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -198,11 +198,11 @@ struct x86_pmu_capability { /* * We model BTS tracing as another fixed-mode PMC. * - * We choose a value in the middle of the fixed event range, since lower + * We choose the value 47 for the fixed index of BTS, since lower * values are used by actual fixed events and higher values are used * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. */ -#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16) +#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15) #define GLOBAL_STATUS_COND_CHG BIT_ULL(63) #define GLOBAL_STATUS_BUFFER_OVF_BIT 62 -- 1.8.3.1