From de9609005a87dd69e34d521eedef64bb45d45f41 Mon Sep 17 00:00:00 2001
From: Shaozhengchao <shaozhengchao@huawei.com>
Date: Tue, 17 Dec 2019 13:45:25 +0800
Subject: [PATCH 2784/2944] openeuler: net/hinic: modify nic_layer comment

commit 474941c7fafbab1a240d7f02a08b396b0f524517 openEuler-1.0

driver inclusion
category:bugfix
bugzilla:4472
CVE:NA

-----------------------------------------------------------------------

modify nic_layer comment

Signed-off-by: Shaozhengchao <shaozhengchao@huawei.com>
Reviewed-by: Luoshaokai <luoshaokai@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Xin Hao <haoxing990@gmail.com>
Reviewed-by: Baolin Wang <baolin.wang@openanolis.org>
---
 .../net/ethernet/huawei/hinic/hinic_dbgtool_knl.c  |  65 +++++----
 .../net/ethernet/huawei/hinic/hinic_dbgtool_knl.h  |   4 +-
 drivers/net/ethernet/huawei/hinic/hinic_dcb.c      |   4 +-
 drivers/net/ethernet/huawei/hinic/hinic_dcb.h      |   2 +-
 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c  |   4 +-
 drivers/net/ethernet/huawei/hinic/hinic_hw.h       |  20 ++-
 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h  | 145 ++++++++++-----------
 drivers/net/ethernet/huawei/hinic/hinic_lld.c      |  18 ++-
 drivers/net/ethernet/huawei/hinic/hinic_lld.h      |   4 +-
 drivers/net/ethernet/huawei/hinic/hinic_main.c     |   2 +-
 drivers/net/ethernet/huawei/hinic/hinic_nic_cfg.h  |   2 +-
 drivers/net/ethernet/huawei/hinic/hinic_nic_io.h   |  16 +--
 drivers/net/ethernet/huawei/hinic/hinic_nictool.c  |   6 +-
 drivers/net/ethernet/huawei/hinic/hinic_qe_def.h   |  74 +++++------
 drivers/net/ethernet/huawei/hinic/hinic_rx.h       |   2 +-
 drivers/net/ethernet/huawei/hinic/hinic_sriov.c    |   2 +-
 16 files changed, 180 insertions(+), 190 deletions(-)

diff --git a/drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.c b/drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.c
index fb915fb..1c9c469 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.c
@@ -47,7 +47,6 @@ struct ffm_intr_info {
 };
 
 #define DBGTOOL_MSG_MAX_SIZE	2048ULL
-
 #define HINIC_SELF_CMD_UP2PF_FFM		0x26
 
 void *g_card_node_array[MAX_CARD_NUM] = {0};
@@ -57,7 +56,7 @@ struct ffm_intr_info {
 struct mutex	g_addr_lock;
 int card_id;
 
-/* dbgtool character device name, class name, dev path*/
+/* dbgtool character device name, class name, dev path */
 #define CHR_DEV_DBGTOOL "dbgtool_chr_dev"
 #define CLASS_DBGTOOL "dbgtool_class"
 #define DBGTOOL_DEV_PATH "/dev/dbgtool_chr_dev"
@@ -154,7 +153,7 @@ int hinic_mem_mmap(struct file *filp, struct vm_area_struct *vma)
  * @para: the dbgtool parameter
  * @g_func_handle_array: global function handle
  * Return: 0 - success, negative - failure
- **/
+ */
 long dbgtool_knl_api_cmd_read(struct dbgtool_param *para,
 			      void **g_func_handle_array)
 {
@@ -172,14 +171,14 @@ long dbgtool_knl_api_cmd_read(struct dbgtool_param *para,
 		return -EFAULT;
 	}
 
-	/* obtaining pf_id chipif pointer*/
+	/* obtaining pf_id chipif pointer */
 	hwdev = g_func_handle_array[pf_id];
 	if (!hwdev) {
 		pr_err("PF id(0x%x) handle null in api cmd read\n", pf_id);
 		return -EFAULT;
 	}
 
-	/* alloc cmd and ack memory*/
+	/* alloc cmd and ack memory */
 	size = para->param.api_rd.size;
 	if (para->param.api_rd.size == 0 || size > DBGTOOL_MSG_MAX_SIZE) {
 		pr_err("Read cmd size invalid or more than 2M\n");
@@ -219,7 +218,7 @@ long dbgtool_knl_api_cmd_read(struct dbgtool_param *para,
 		goto api_rd_fail;
 	}
 
-	/* Copy the contents of the ack to the user state*/
+	/* Copy the contents of the ack to the user state */
 	if (copy_to_user(para->param.api_rd.ack, ack, ack_size)) {
 		pr_err("Copy ack to user fail\n");
 		ret = -EFAULT;
@@ -237,7 +236,7 @@ long dbgtool_knl_api_cmd_read(struct dbgtool_param *para,
  * @para: the dbgtool parameter
  * @g_func_handle_array: global function handle
  * Return: 0 - success, negative - failure
- **/
+ */
 long dbgtool_knl_api_cmd_write(struct dbgtool_param *para,
 			       void **g_func_handle_array)
 {
@@ -260,7 +259,7 @@ long dbgtool_knl_api_cmd_write(struct dbgtool_param *para,
 		return -EFAULT;
 	}
 
-	/* alloc cmd memory*/
+	/* alloc cmd memory */
 	size = para->param.api_wr.size;
 	if (para->param.api_wr.size == 0 || size > DBGTOOL_MSG_MAX_SIZE) {
 		pr_err("Write cmd size invalid or more than 2M\n");
@@ -272,14 +271,14 @@ long dbgtool_knl_api_cmd_write(struct dbgtool_param *para,
 		return -ENOMEM;
 	}
 
-	/* cmd content copied from user-mode*/
+	/* cmd content copied from user-mode */
 	if (copy_from_user(cmd, para->param.api_wr.cmd, (unsigned long)size)) {
 		pr_err("Copy cmd from user fail\n");
 		ret = -EFAULT;
 		goto copy_user_cmd_fail;
 	}
 
-	/* api cmd interface is invoked to write the content*/
+	/* api cmd interface is invoked to write the content */
 	ret = hinic_api_cmd_write_nack(hwdev, para->param.api_wr.dest,
 				       cmd, size);
 	if (ret)
@@ -301,7 +300,7 @@ void chipif_get_all_pf_dev_info(struct pf_dev_info *dev_info, int card_idx,
 		return;
 	}
 
-	/* pf at most 16*/
+	/* pf at most 16 */
 	for (func_idx = 0; func_idx < 16; func_idx++) {
 		hwdev = (struct hinic_hwdev *)g_func_handle_array[func_idx];
 
@@ -334,7 +333,7 @@ void chipif_get_all_pf_dev_info(struct pf_dev_info *dev_info, int card_idx,
  * @para: the dbgtool parameter
  * @g_func_handle_array: global function handle
  * Return: 0 - success, negative - failure
- **/
+ */
 long dbgtool_knl_pf_dev_info_get(struct dbgtool_param *para,
 				 void **g_func_handle_array)
 {
@@ -377,7 +376,7 @@ long dbgtool_knl_pf_dev_info_get(struct dbgtool_param *para,
 
 	chipif_get_all_pf_dev_info(dev_info, card_id, g_func_handle_array);
 
-	/* Copy the dev_info to user mode*/
+	/* Copy the dev_info to user mode */
 	if (copy_to_user(para->param.dev_info, dev_info,
 			 (unsigned int)sizeof(dev_info))) {
 		pr_err("Copy dev_info to user fail\n");
@@ -392,11 +391,11 @@ long dbgtool_knl_pf_dev_info_get(struct dbgtool_param *para,
  * @para: the dbgtool parameter
  * @dbgtool_info: the dbgtool info
  * Return: 0 - success, negative - failure
- **/
+ */
 long dbgtool_knl_ffm_info_rd(struct dbgtool_param *para,
 			     struct dbgtool_k_glb_info *dbgtool_info)
 {
-	/* Copy the ffm_info to user mode*/
+	/* Copy the ffm_info to user mode */
 	if (copy_to_user(para->param.ffm_rd, dbgtool_info->ffm,
 			 (unsigned int)sizeof(struct ffm_record_info))) {
 		pr_err("Copy ffm_info to user fail\n");
@@ -410,7 +409,7 @@ long dbgtool_knl_ffm_info_rd(struct dbgtool_param *para,
  * dbgtool_knl_ffm_info_clr - Clear FFM information
  * @para: unused
  * @dbgtool_info: the dbgtool info
- **/
+ */
 void dbgtool_knl_ffm_info_clr(struct dbgtool_param *para,
 			      struct dbgtool_k_glb_info *dbgtool_info)
 {
@@ -422,7 +421,7 @@ void dbgtool_knl_ffm_info_clr(struct dbgtool_param *para,
  * @para: the dbgtool parameter
  * @g_func_handle_array: global function handle
  * Return: 0 - success, negative - failure
- **/
+ */
 long dbgtool_knl_msg_to_up(struct dbgtool_param *para,
 			   void **g_func_handle_array)
 {
@@ -439,7 +438,7 @@ long dbgtool_knl_msg_to_up(struct dbgtool_param *para,
 	}
 
 	pf_id = para->param.msg2up.pf_id;
-	/* pf at most 16*/
+	/* pf at most 16 */
 	if (pf_id >= 16) {
 		pr_err("PF id(0x%x) too big in message to mgmt\n", pf_id);
 		return -EFAULT;
@@ -450,7 +449,7 @@ long dbgtool_knl_msg_to_up(struct dbgtool_param *para,
 		return -EFAULT;
 	}
 
-	/* alloc buf_in and buf_out memory, apply for 2K*/
+	/* alloc buf_in and buf_out memory, apply for 2K */
 	buf_in = kzalloc(DBGTOOL_MSG_MAX_SIZE, GFP_KERNEL);
 	if (!buf_in) {
 		pr_err("Alloc buf_in mem fail\n");
@@ -464,7 +463,7 @@ long dbgtool_knl_msg_to_up(struct dbgtool_param *para,
 		goto alloc_buf_out_mem_fail;
 	}
 
-	/* copy buf_in from the user state*/
+	/* copy buf_in from the user state */
 	if (copy_from_user(buf_in, para->param.msg2up.buf_in,
 			   (unsigned long)para->param.msg2up.in_size)) {
 		pr_err("Copy buf_in from user fail\n");
@@ -473,7 +472,7 @@ long dbgtool_knl_msg_to_up(struct dbgtool_param *para,
 	}
 
 	out_size = DBGTOOL_MSG_MAX_SIZE;
-	/* Invoke the pf2up communication interface*/
+	/* Invoke the pf2up communication interface */
 	ret = hinic_msg_to_mgmt_sync(g_func_handle_array[pf_id],
 				     para->param.msg2up.mod,
 				     para->param.msg2up.cmd,
@@ -482,12 +481,10 @@ long dbgtool_knl_msg_to_up(struct dbgtool_param *para,
 				     buf_out,
 				     &out_size,
 				     0);
-	/* 50s timeout time is sufficient*/
-
 	if (ret)
 		goto msg_2_up_fail;
 
-	/* Copy the out_size and buf_out content to user mode*/
+	/* Copy the out_size and buf_out content to user mode */
 	if (copy_to_user(para->param.msg2up.out_size, &out_size,
 			 (unsigned int)sizeof(out_size))) {
 		pr_err("Copy out_size to user fail\n");
@@ -542,7 +539,7 @@ long dbgtool_knl_free_mem(int id)
  * dbgtool_knl_unlocked_ioctl - dbgtool ioctl entry
  * @pfile: the pointer to file
  * @cmd: the command type
- **/
+ */
 long dbgtool_knl_unlocked_ioctl(struct file *pfile,
 				unsigned int cmd,
 				unsigned long arg)
@@ -622,10 +619,8 @@ long dbgtool_knl_unlocked_ioctl(struct file *pfile,
  * ffm_intr_msg_record - FFM interruption records sent up
  * @handle: the function handle
  * @buf_in: the pointer to input buffer
- * @in_size: the input buffer size
- * @buf_out: the pointer to output buffer
- * @out_size: the output buffer size
- **/
+ * @buf_out: the pointer to outputput buffer
+ */
 void ffm_intr_msg_record(void *handle, void *buf_in, u16 in_size,
 			 void *buf_out, u16 *out_size)
 {
@@ -682,10 +677,10 @@ void ffm_intr_msg_record(void *handle, void *buf_in, u16 in_size,
 		dbgtool_info->ffm->ffm[ffm_idx].err_csr_value =
 						intr->err_csr_value;
 
-		/* Obtain the current UTC time*/
+		/* Obtain the current UTC time */
 		 do_gettimeofday(&txc.time);
 
-		/* Calculate the time in date value to tm*/
+		/* Calculate the time in date value to tm */
 		 rtc_time_to_tm((unsigned long)txc.time.tv_sec +
 				60 * 60 * 8, &rctm);
 
@@ -721,7 +716,7 @@ void ffm_intr_msg_record(void *handle, void *buf_in, u16 in_size,
  * @hwdev: the pointer to hardware device
  * @chip_node: the pointer to card node
  * Return: 0 - success, negative - failure
- **/
+ */
 int dbgtool_knl_init(void *vhwdev, void *chip_node)
 {
 	int ret = 0;
@@ -760,7 +755,7 @@ int dbgtool_knl_init(void *vhwdev, void *chip_node)
 	}
 	chip_info->dbgtool_info = dbgtool_info;
 
-	/*FFM init*/
+	/* FFM init */
 	dbgtool_info->ffm = (struct ffm_record_info *)
 				kzalloc(sizeof(struct ffm_record_info),
 					GFP_KERNEL);
@@ -855,7 +850,7 @@ int dbgtool_knl_init(void *vhwdev, void *chip_node)
  * dbgtool_knl_deinit - dbgtool character device deinit
  * @hwdev: the pointer to hardware device
  * @chip_node: the pointer to card node
- **/
+ */
 void dbgtool_knl_deinit(void *vhwdev, void *chip_node)
 {
 	struct dbgtool_k_glb_info *dbgtool_info;
@@ -885,7 +880,7 @@ void dbgtool_knl_deinit(void *vhwdev, void *chip_node)
 	g_card_node_array[id] = NULL;
 
 	dbgtool_info = chip_info->dbgtool_info;
-	/*FFM deinit*/
+	/* FFM deinit */
 	kfree(dbgtool_info->ffm);
 	dbgtool_info->ffm = NULL;
 
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.h b/drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.h
index 33aaca1..6cd33d7 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.h
@@ -61,7 +61,7 @@ struct pf_dev_info {
 	u64 phy_addr;
 };
 
-/* Interrupt at most records, interrupt will be recorded in the FFM*/
+/* Interrupt at most records, interrupt will be recorded in the FFM */
 #define FFM_RECORD_NUM_MAX 64
 
 struct ffm_intr_tm_info {
@@ -87,7 +87,7 @@ struct ffm_record_info {
 };
 
 struct msg_2_up {
-	u8 pf_id;   /* which pf sends messages to the up*/
+	u8 pf_id;   /* which pf sends messages to the up */
 	u8 mod;
 	u8 cmd;
 	void *buf_in;
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_dcb.c b/drivers/net/ethernet/huawei/hinic/hinic_dcb.c
index 75a769b..96e99e1 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_dcb.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_dcb.c
@@ -216,7 +216,7 @@ int hinic_dcb_init(struct hinic_nic_dev *nic_dev)
 	for (i = 0; i < HINIC_DCB_COS_MAX; i++) {
 		if (cos_valid_bitmap & BIT(i)) {
 			support_cos++;
-			default_cos = i;/* Find max cos id as default cos */
+			default_cos = i; /* Find max cos id as default cos */
 		}
 	}
 
@@ -1532,7 +1532,7 @@ static u8 hinic_dcbnl_setdcbx(struct net_device *netdev, u8 mode)
 	.ieee_getpfc	= hinic_dcbnl_ieee_get_pfc,
 	.ieee_setpfc	= hinic_dcbnl_ieee_set_pfc,
 
-	/*CEE std*/
+	/* CEE std */
 	.getstate	= hinic_dcbnl_get_state,
 	.setstate	= hinic_dcbnl_set_state,
 	.getpermhwaddr	= hinic_dcbnl_get_perm_hw_addr,
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_dcb.h b/drivers/net/ethernet/huawei/hinic/hinic_dcb.h
index 056b722..89074a7 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_dcb.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_dcb.h
@@ -19,7 +19,7 @@
 #define HINIC_DCB_CFG_TX	0
 #define HINIC_DCB_CFG_RX	1
 
-/*IEEE8021QAZ Transmission selection algorithm identifiers */
+/* IEEE8021QAZ Transmission selection algorithm identifiers */
 #define IEEE8021Q_TSA_STRICT	0x0
 #define IEEE8021Q_TSA_CBSHAPER	0x1
 #define IEEE8021Q_TSA_ETS	0x2
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c b/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c
index ad9faab..711ea53 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c
@@ -991,7 +991,7 @@ static int hinic_set_ringparam(struct net_device *netdev,
 
 	if (new_sq_depth == nic_dev->sq_depth &&
 	    new_rq_depth == nic_dev->rq_depth)
-		return 0;	/* nothing will do */
+		return 0;
 
 	if (test_bit(HINIC_BP_ENABLE, &nic_dev->flags) &&
 	    new_rq_depth <= nic_dev->bp_upper_thd) {
@@ -2230,7 +2230,7 @@ static int __set_rss_rxfh(struct net_device *netdev,
 			/* We request double spaces for the hash key,
 			 * the second one holds the key of Big Edian
 			 * format.
-			*/
+			 */
 			nic_dev->rss_hkey_user =
 				kzalloc(HINIC_RSS_KEY_SIZE * 2, GFP_KERNEL);
 
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_hw.h b/drivers/net/ethernet/huawei/hinic/hinic_hw.h
index f6fb9d2..8876c29 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_hw.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_hw.h
@@ -32,7 +32,7 @@
 
 enum hinic_mod_type {
 	HINIC_MOD_COMM = 0,	/* HW communication module */
-	HINIC_MOD_L2NIC = 1,	/* L2NIC module*/
+	HINIC_MOD_L2NIC = 1,	/* L2NIC module */
 	HINIC_MOD_ROCE = 2,
 	HINIC_MOD_IWARP = 3,
 	HINIC_MOD_TOE = 4,
@@ -111,8 +111,7 @@ int hinic_cmdq_detail_resp(void *hwdev, enum hinic_ack_type ack_type,
 			   struct hinic_cmd_buf *buf_in,
 			   struct hinic_cmd_buf *buf_out, u32 timeout);
 
-/* PF/VF send cmd to ucode by cmdq, and return immediately
- */
+/* PF/VF send cmd to ucode by cmdq, and return immediately */
 int hinic_cmdq_async(void *hwdev, enum hinic_ack_type ack_type,
 		     enum hinic_mod_type mod, u8 cmd,
 		     struct hinic_cmd_buf *buf_in);
@@ -120,7 +119,7 @@ int hinic_cmdq_async(void *hwdev, enum hinic_ack_type ack_type,
 int hinic_ppf_tmr_start(void *hwdev);
 int hinic_ppf_tmr_stop(void *hwdev);
 
-/*CLP*/
+/* CLP */
 int hinic_clp_to_mgmt(void *hwdev, enum hinic_mod_type mod, u8 cmd,
 		      void *buf_in, u16 in_size,
 		      void *buf_out, u16 *out_size);
@@ -204,7 +203,7 @@ int hinic_get_interrupt_cfg(void *hwdev,
 int hinic_set_interrupt_cfg(void *hwdev,
 			    struct nic_interrupt_info interrupt_info);
 
-/* The driver code implementation interface*/
+/* The driver code implementation interface */
 void hinic_misx_intr_clear_resend_bit(void *hwdev,
 				      u16 msix_idx, u8 clear_resend_en);
 
@@ -229,7 +228,7 @@ struct hinic_sq_attr {
 int hinic_func_tmr_bitmap_set(void *hwdev, bool enable);
 
 struct hinic_init_para {
-	/* Record hinic_pcidev or NDIS_Adapter pointer address*/
+	/* Record hinic_pcidev or NDIS_Adapter pointer address */
 	void *adapter_hdl;
 	/* Record pcidev or Handler pointer address
 	 * for example: ioremap interface input parameter
@@ -240,12 +239,12 @@ struct hinic_init_para {
 	 */
 	void *dev_hdl;
 
-	void *cfg_reg_base;	/* Configure virtual address, bar0/1*/
+	void *cfg_reg_base;	/* Configure virtual address, bar0/1 */
 	/* interrupt configuration register address, bar2/3 */
 	void *intr_reg_base;
 	u64 db_base_phy;
-	void *db_base;	/* the doorbell address, bar4/5 higher 4M space*/
-	void *dwqe_mapping;/* direct wqe 4M, follow the doorbell address space*/
+	void *db_base;	/* the doorbell address, bar4/5 higher 4M space */
+	void *dwqe_mapping; /* direct wqe 4M, follow the doorbell address */
 	void **hwdev;
 	void *chip_node;
 	/* In bmgw x86 host, driver can't send message to mgmt cpu directly,
@@ -468,8 +467,7 @@ struct hinic_fault_sw_mgmt {
 		u16 err_type;
 		u32 err_csr_addr;
 		u32 err_csr_value;
-		/* func_id valid only err_level==FAULT_LEVEL_SERIOUS_FLR
-		 */
+		/* func_id valid only err_level==FAULT_LEVEL_SERIOUS_FLR */
 		u16 func_id;
 		u16 rsvd2;
 	} chip;
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h b/drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h
index 5f5044e..272a3d9 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h
@@ -59,7 +59,7 @@ enum hinic_service_type {
  *	 enable the VMDq: Each PF/VF at most 1K SQ
  */
 struct nic_service_cap {
-	/* PF resources*/
+	/* PF resources */
 	u16 max_sqs;
 	u16 max_rqs;
 
@@ -113,7 +113,7 @@ struct dev_roce_svc_own_cap {
 	u32 max_srq_sge;
 	u32 srqc_entry_sz;
 
-	u32 max_msg_sz;/* Message size 2GB*/
+	u32 max_msg_sz; /* Message size 2GB */
 
 	u8 num_cos;
 };
@@ -152,7 +152,7 @@ struct dev_iwarp_svc_own_cap {
 	u32 max_ackq_depth;
 	u32 ackq_entry_size;   /* 16B */
 
-	u32 max_msg_sz;        /* Message size 1GB*/
+	u32 max_msg_sz;        /* Message size 1GB */
 
 	u32 max_wqes;           /* 8K */
 	u32 qpc_entry_sz;       /* 1K */
@@ -166,7 +166,7 @@ struct dev_iwarp_svc_own_cap {
 	u8 num_cos;
 };
 
-/* RDMA service capability structure*/
+/* RDMA service capability structure */
 struct dev_rdma_svc_cap {
 	/* ROCE service unique parameter structure */
 	struct dev_roce_svc_own_cap  roce_own_cap;
@@ -189,7 +189,7 @@ enum {
 	RDMA_DEV_CAP_FLAG_APM           = (1 << 9),
 };
 
-/* RDMA services*/
+/* RDMA services */
 struct rdma_service_cap {
 	struct dev_rdma_svc_cap     dev_rdma_cap;
 
@@ -202,8 +202,8 @@ struct rdma_service_cap {
 			 * contain 1, 2, 4, 8, and 16 PA)
 			 */
 
-	u32 reserved_qps;	/* Number of reserved QP*/
-	u32 max_sq_sg;		/* Maximum SGE number of SQ (8)*/
+	u32 reserved_qps;	/* Number of reserved QP */
+	u32 max_sq_sg;		/* Maximum SGE number of SQ (8) */
 	u32 max_sq_desc_sz;	/* WQE maximum size of SQ(1024B), inline maximum
 				 * size if 960B(944B aligned to the 960B),
 				 * 960B=>wqebb alignment=>1024B
@@ -212,13 +212,13 @@ struct rdma_service_cap {
 				 * defined as 64Bytes
 				 */
 
-	u32 max_cqes;		/* Size of the depth of the CQ (64K-1)*/
-	u32 reserved_cqs;	/* Number of reserved CQ*/
-	u32 cqc_entry_sz;	/* Size of the CQC (64B/128B)*/
-	u32 cqe_size;		/* Size of CQE (32B)*/
+	u32 max_cqes;		/* Size of the depth of the CQ (64K-1) */
+	u32 reserved_cqs;	/* Number of reserved CQ */
+	u32 cqc_entry_sz;	/* Size of the CQC (64B/128B) */
+	u32 cqe_size;		/* Size of CQE (32B) */
 
-	u32 reserved_mrws;	/* Number of reserved MR/MR Window*/
-	u32 mpt_entry_sz;	/* MPT table size (64B)*/
+	u32 reserved_mrws;	/* Number of reserved MR/MR Window */
+	u32 mpt_entry_sz;	/* MPT table size (64B) */
 	u32 max_fmr_maps;	/* max MAP of FMR,
 				 * (1 << (32-ilog2(num_mpt)))-1;
 				 */
@@ -226,40 +226,40 @@ struct rdma_service_cap {
 	u32 num_mtts;		/* Number of MTT table (4M),
 				 * is actually MTT seg number
 				 */
-	/* MTT table number of Each MTT seg(3)*/
+	/* MTT table number of Each MTT seg(3) */
 	u32 log_mtt_seg;
-	u32 mtt_entry_sz;      /* MTT table size 8B, including 1 PA(64bits)*/
-	u32 log_rdmarc_seg;    /* table number of each RDMArc seg(3)*/
+	u32 mtt_entry_sz;      /* MTT table size 8B, including 1 PA(64bits) */
+	u32 log_rdmarc_seg;    /* table number of each RDMArc seg(3) */
 
-	/* Timeout time. Formula:Tr=4.096us*2(local_ca_ack_delay), [Tr,4Tr]*/
+	/* Timeout time. Formula:Tr=4.096us*2(local_ca_ack_delay), [Tr,4Tr] */
 	u32 local_ca_ack_delay;
-	u32 num_ports;		/* Physical port number*/
+	u32 num_ports;		/* Physical port number */
 
-	u32 db_page_size;	/* Size of the DB (4KB)*/
-	u32 direct_wqe_size;	/* Size of the DWQE (256B)*/
+	u32 db_page_size;	/* Size of the DB (4KB) */
+	u32 direct_wqe_size;	/* Size of the DWQE (256B) */
 
-	u32 num_pds;		/* Maximum number of PD (128K)*/
+	u32 num_pds;		/* Maximum number of PD (128K) */
 	u32 reserved_pds;	/* Number of reserved PD*/
-	u32 max_xrcds;		/* Maximum number of xrcd (64K)*/
-	u32 reserved_xrcds;	/* Number of reserved xrcd*/
+	u32 max_xrcds;		/* Maximum number of xrcd (64K) */
+	u32 reserved_xrcds;	/* Number of reserved xrcd */
 
-	u32 max_gid_per_port;	/* gid number (16) of each port*/
+	u32 max_gid_per_port;	/* gid number (16) of each port */
 	u32 gid_entry_sz;	/* RoCE v2 GID table is 32B,
 				 * compatible RoCE v1 expansion
 				 */
 
 	u32 reserved_lkey;	/* local_dma_lkey */
-	u32 num_comp_vectors;	/* Number of complete vector (32)*/
-	u32 page_size_cap;	/* Supports 4K,8K,64K,256K,1M and 4M page_size*/
+	u32 num_comp_vectors;	/* Number of complete vector (32) */
+	u32 page_size_cap;	/* Supports 4K,8K,64K,256K,1M,4M page_size */
 
-	u32 flags;		/* RDMA some identity*/
-	u32 max_frpl_len;	/* Maximum number of pages frmr registration*/
-	u32 max_pkeys;		/* Number of supported pkey group*/
+	u32 flags;		/* RDMA some identity */
+	u32 max_frpl_len;	/* Maximum number of pages frmr registration */
+	u32 max_pkeys;		/* Number of supported pkey group */
 };
 
-/* PF/VF FCoE service resource structure defined*/
+/* PF/VF FCoE service resource structure defined */
 struct dev_fcoe_svc_cap {
-	/* PF resources*/
+	/* PF resources */
 	u32 max_qps;
 	u32 max_cqs;
 	u32 max_srqs;
@@ -274,7 +274,7 @@ struct dev_fcoe_svc_cap {
 	u8 vp_id_end;
 };
 
-/* FCoE services*/
+/* FCoE services */
 struct fcoe_service_cap {
 	struct dev_fcoe_svc_cap     dev_fcoe_cap;
 
@@ -295,7 +295,7 @@ struct fcoe_service_cap {
 /* PF/VF ToE service resource structure */
 struct dev_toe_svc_cap {
 	/* PF resources*/
-	u32 max_pctxs; /* Parent Context: max specifications 1M*/
+	u32 max_pctxs; /* Parent Context: max specifications 1M */
 	u32 max_cqs;
 	u32 max_srqs;
 	u32 srq_id_start;
@@ -303,7 +303,7 @@ struct dev_toe_svc_cap {
 	u8 num_cos;
 };
 
-/* ToE services*/
+/* ToE services */
 struct toe_service_cap {
 	struct dev_toe_svc_cap      dev_toe_cap;
 
@@ -312,20 +312,20 @@ struct toe_service_cap {
 	u32 scqc_sz;/* 64B */
 };
 
-/* PF FC service resource structure defined*/
+/* PF FC service resource structure defined */
 struct dev_fc_svc_cap {
 	/* PF Parent QPC */
-	u32 max_parent_qpc_num; /* max number is 2048*/
+	u32 max_parent_qpc_num; /* max number is 2048 */
 
 	/* PF Child QPC */
-	u32 max_child_qpc_num;  /* max number is 2048*/
+	u32 max_child_qpc_num;  /* max number is 2048 */
 	u32 child_qpc_id_start;
 
 	/* PF SCQ */
 	u32 scq_num;            /* 16 */
 
 	/* PF supports SRQ*/
-	u32 srq_num;            /* Number of SRQ is 2*/
+	u32 srq_num;            /* Number of SRQ is 2 */
 
 	u8 vp_id_start;
 	u8 vp_id_end;
@@ -342,29 +342,29 @@ struct fc_service_cap {
 	u32 child_qpc_size;     /* 256B */
 
 	/* SQ */
-	u32 sqe_size;           /* 128B(in linked list mode)*/
+	u32 sqe_size;           /* 128B(in linked list mode) */
 
 	/* SCQ */
-	u32 scqc_size;          /* Size of the Context 32B*/
+	u32 scqc_size;          /* Size of the Context 32B */
 	u32 scqe_size;          /* 64B */
 
 	/* SRQ */
-	u32 srqc_size;         /* Size of SRQ Context (64B)*/
+	u32 srqc_size;         /* Size of SRQ Context (64B) */
 	u32 srqe_size;         /* 32B */
 };
 
-/* PF OVS service resource structure defined*/
+/* PF OVS service resource structure defined */
 struct dev_ovs_svc_cap {
-	/* PF resources*/
-	u32 max_pctxs; /* Parent Context: max specifications 1M*/
+	/* PF resources */
+	u32 max_pctxs; /* Parent Context: max specifications 1M */
 	u32 max_cqs;
 
-	/* VF resources*/
-	u32 vf_max_pctxs; /* Parent Context: max specifications 1M*/
+	/* VF resources */
+	u32 vf_max_pctxs; /* Parent Context: max specifications 1M */
 	u32 vf_max_cqs;
 };
 
-/* OVS services*/
+/* OVS services */
 struct ovs_service_cap {
 	struct dev_ovs_svc_cap dev_ovs_cap;
 
@@ -375,16 +375,16 @@ struct ovs_service_cap {
 
 /* PF ACL service resource structure */
 struct dev_acl_svc_cap {
-	/* PF resources*/
-	u32 max_pctxs; /* Parent Context: max specifications 1M*/
+	/* PF resources */
+	u32 max_pctxs; /* Parent Context: max specifications 1M */
 	u32 max_cqs;
 
-	/* VF resources*/
-	u32 vf_max_pctxs; /* Parent Context: max specifications 1M*/
+	/* VF resources */
+	u32 vf_max_pctxs; /* Parent Context: max specifications 1M */
 	u32 vf_max_cqs;
 };
 
-/* ACL services*/
+/* ACL services */
 struct acl_service_cap {
 	struct dev_acl_svc_cap    dev_acl_cap;
 
@@ -396,7 +396,7 @@ struct acl_service_cap {
 bool hinic_support_nic(void *hwdev, struct nic_service_cap *cap);
 bool hinic_support_roce(void *hwdev, struct rdma_service_cap *cap);
 bool hinic_support_fcoe(void *hwdev, struct fcoe_service_cap *cap);
-/* PPF support,PF not support*/
+/* PPF support,PF not support */
 bool hinic_support_toe(void *hwdev, struct toe_service_cap *cap);
 bool hinic_support_iwarp(void *hwdev, struct rdma_service_cap *cap);
 bool hinic_support_fc(void *hwdev, struct fc_service_cap *cap);
@@ -413,24 +413,24 @@ struct acl_service_cap {
 bool hinic_get_fcoe_enable(void *hwdev);
 bool hinic_get_stateful_enable(void *hwdev);
 
-/* Service interface for obtaining service_cap public fields*/
-/* Obtain service_cap.host_oq_id_mask_val*/
+/* Service interface for obtaining service_cap public fields */
+/* Obtain service_cap.host_oq_id_mask_val */
 u8 hinic_host_oq_id_mask(void *hwdev);
-u8 hinic_host_id(void *hwdev);/* Obtain service_cap.host_id*/
-/* Obtain service_cap.host_total_function*/
+u8 hinic_host_id(void *hwdev);/* Obtain service_cap.host_id */
+/* Obtain service_cap.host_total_function */
 u16 hinic_host_total_func(void *hwdev);
-/* Obtain service_cap.nic_cap.dev_nic_cap.max_sqs*/
+/* Obtain service_cap.nic_cap.dev_nic_cap.max_sqs */
 u16 hinic_func_max_nic_qnum(void *hwdev);
-/* Obtain service_cap.dev_cap.max_sqs*/
+/* Obtain service_cap.dev_cap.max_sqs */
 u16 hinic_func_max_qnum(void *hwdev);
-u8 hinic_ep_id(void *hwdev);/* Obtain service_cap.ep_id*/
-u8 hinic_er_id(void *hwdev);/* Obtain service_cap.er_id*/
-u8 hinic_physical_port_id(void *hwdev);/* Obtain service_cap.port_id*/
-u8 hinic_func_max_vf(void *hwdev);/* Obtain service_cap.max_vf*/
-u32 hinic_func_pf_num(void *hwdev);/* Obtain service_cap.pf_num*/
+u8 hinic_ep_id(void *hwdev);/* Obtain service_cap.ep_id */
+u8 hinic_er_id(void *hwdev);/* Obtain service_cap.er_id */
+u8 hinic_physical_port_id(void *hwdev);/* Obtain service_cap.port_id */
+u8 hinic_func_max_vf(void *hwdev);/* Obtain service_cap.max_vf */
+u32 hinic_func_pf_num(void *hwdev);/* Obtain service_cap.pf_num */
 u8 hinic_max_num_cos(void *hwdev);
 u8 hinic_cos_valid_bitmap(void *hwdev);
-u8 hinic_net_port_mode(void *hwdev);/* Obtain service_cap.net_port_mode*/
+u8 hinic_net_port_mode(void *hwdev);/* Obtain service_cap.net_port_mode */
 
 /* The following information is obtained from the bar space
  * which is recorded by SDK layer.
@@ -438,7 +438,7 @@ struct acl_service_cap {
  */
 /* func_attr.glb_func_idx, global function index */
 u16 hinic_global_func_id(void *hwdev);
-/* func_attr.intr_num, MSI-X table entry in function*/
+/* func_attr.intr_num, MSI-X table entry in function */
 u16 hinic_intr_num(void *hwdev);
 enum intr_type {
 	INTR_TYPE_MSIX,
@@ -486,7 +486,7 @@ enum hinic_msix_state {
 void hinic_set_msix_state(void *hwdev, u16 msix_idx,
 			  enum hinic_msix_state flag);
 
-/* Define the version information structure*/
+/* Define the version information structure */
 struct dev_version_info {
 	u8 up_ver;	/* uP version, directly read from uP
 			 * is not configured to file
@@ -494,18 +494,17 @@ struct dev_version_info {
 	u8 ucode_ver;	/* The microcode version,
 			 * read through the CMDq from microcode
 			 */
-	u8 cfg_file_ver;/* uP configuration file version*/
-	u8 sdk_ver;	/* SDK driver version*/
-	u8 hw_ver;	/* Hardware version*/
+	u8 cfg_file_ver;/* uP configuration file version */
+	u8 sdk_ver;	/* SDK driver version */
+	u8 hw_ver;	/* Hardware version */
 };
 
-/* Obtain service_cap.dev_version_info
- */
+/* Obtain service_cap.dev_version_info */
 int hinic_dev_ver_info(void *hwdev, struct dev_version_info *ver);
 
 int hinic_vector_to_eqn(void *hwdev, enum hinic_service_type type, int vector);
 
-/* Defines the IRQ information structure*/
+/* Defines the IRQ information structure */
 struct irq_info {
 	u16 msix_entry_idx; /* IRQ corresponding index number */
 	u32 irq_id;         /* the IRQ number from OS */
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_lld.c b/drivers/net/ethernet/huawei/hinic/hinic_lld.c
index a511fb2..357e050 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_lld.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_lld.c
@@ -94,7 +94,7 @@ enum {
 	HINIC_FUNC_PRB_DELAY = BIT(2),
 };
 
-/* Structure pcidev private*/
+/* Structure pcidev private */
 struct hinic_pcidev {
 	struct pci_dev *pcidev;
 	void *hwdev;
@@ -821,7 +821,7 @@ static struct hinic_pcidev *hinic_get_pcidev_by_chip_name(char *ifname)
 {
 	struct hinic_pcidev *dev, *dev_hw_init;
 
-	/*find hw init device first*/
+	/* find hw init device first */
 	dev_hw_init = _get_pcidev_by_chip_name(ifname, TYPE_UNKNOWN);
 	if (dev_hw_init) {
 		if (hinic_func_type(dev_hw_init->hwdev) == TYPE_PPF)
@@ -1072,9 +1072,8 @@ void *hinic_get_uld_by_chip_name(char *ifname, enum hinic_service_type type)
 	struct hinic_pcidev *dev;
 
 	/* support search hwdev by chip name, net device name,
-	 * or fc device name
+	 * or fc device name, Find pcidev by chip_name first
 	 */
-	/* Find pcidev by chip_name first */
 	dev = hinic_get_pcidev_by_chip_name(ifname);
 	if (dev)
 		return dev->uld_dev[type];
@@ -1996,7 +1995,7 @@ static bool hinic_get_vf_load_state(struct pci_dev *pdev)
 	if (!pdev->is_virtfn)
 		return false;
 
-	/*vf used in vm*/
+	/* vf used in vm */
 	if (pci_is_root_bus(pdev->bus))
 		return disable_vf_load;
 
@@ -2042,7 +2041,6 @@ static void hinic_set_vf_load_state(struct hinic_pcidev *pci_adapter,
 int hinic_ovs_set_vf_load_state(struct pci_dev *pdev)
 {
 	struct hinic_pcidev *pci_adapter;
-
 	if (!pdev) {
 		pr_err("pdev is null.\n");
 		return -EINVAL;
@@ -2207,8 +2205,8 @@ static void hinic_notify_ppf_reg(struct hinic_pcidev *pci_adapter)
 /**
  * cfg_order_reg - when cpu model is haswell or broadwell, should configure dma
  * order register to zero
- * @pci_adapter: pci_adapter
- **/
+ * @pci_adapter: pci adapter
+ */
 /*lint -save -e40 */
 void cfg_order_reg(struct hinic_pcidev *pci_adapter)
 {
@@ -2292,7 +2290,7 @@ static int hinic_func_init(struct pci_dev *pdev,
 	if (!HINIC_FUNC_IS_VF(pci_adapter->hwdev))
 		hinic_sync_time_to_fmw(pci_adapter);
 
-	/*dbgtool init*/
+	/* dbgtool init */
 	lld_lock_chip_node();
 	err = dbgtool_knl_init(pci_adapter->hwdev, pci_adapter->chip_node);
 	if (err) {
@@ -2516,7 +2514,7 @@ static void slave_host_init_delay_work(struct work_struct *work)
 		return;
 	}
 
-	/*Make sure the PPF must be the first one.*/
+	/* Make sure the PPF must be the first one */
 	lld_dev_hold();
 	list_for_each_entry(ppf_pcidev, &chip_node->func_list, node) {
 		if (ppf_pcidev &&
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_lld.h b/drivers/net/ethernet/huawei/hinic/hinic_lld.h
index 844fb5f2..f257ca5 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_lld.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_lld.h
@@ -68,9 +68,9 @@ int hinic_register_uld(enum hinic_service_type uld_type,
 void *hinic_get_ppf_uld_by_pdev(struct pci_dev *pdev,
 				enum hinic_service_type type);
 
-/* used for TOE/IWARP*/
+/* used for TOE/IWARP */
 struct net_device *hinic_get_netdev_by_lld(struct hinic_lld_dev *lld_dev);
-/* used for TOE/IWARP*/
+/* used for TOE/IWARP */
 void *hinic_get_hwdev_by_netdev(struct net_device *netdev);
 
 struct net_device *hinic_get_netdev_by_pcidev(struct pci_dev *pdev);
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_main.c b/drivers/net/ethernet/huawei/hinic/hinic_main.c
index 157563a..ddabee71 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_main.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_main.c
@@ -937,7 +937,7 @@ int hinic_open(struct net_device *netdev)
 
 vport_enable_err:
 	hinic_flush_sq_res(nic_dev->hwdev);
-	/* After set vport disable 100ms, no packets will be send to host*/
+	/* After set vport disable 100ms, no packets will be send to host */
 	msleep(100);
 	hinic_qps_irq_deinit(nic_dev);
 
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_nic_cfg.h b/drivers/net/ethernet/huawei/hinic/hinic_nic_cfg.h
index 0ea04eb..7bb6d1c 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_nic_cfg.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_nic_cfg.h
@@ -468,7 +468,7 @@ int hinic_get_link_mode(void *hwdev, enum hinic_link_mode *supported,
 /* Win NIC used */
 int hinic_set_rx_lro(void *hwdev, u8 ipv4_en, u8 ipv6_en, u8 max_wqe_num);
 
-/* Related command dcbtool*/
+/* Related command dcbtool */
 int hinic_dcb_set_pfc(void *hwdev, u8 pfc_en, u8 pfc_bitmap);
 
 int hinic_dcb_get_pfc(void *hwdev, u8 *pfc_en_bitmap);
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_nic_io.h b/drivers/net/ethernet/huawei/hinic/hinic_nic_io.h
index e52f99f..c38e356 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_nic_io.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_nic_io.h
@@ -20,7 +20,7 @@
 #include "hinic_qe_def.h"
 
 #define HINIC_RX_BUF_SHIFT	11
-#define HINIC_RX_BUF_LEN	2048	/*buffer len must be 2^n*/
+#define HINIC_RX_BUF_LEN	2048	/* buffer len must be 2^n */
 
 #define SQ_CTRL_SET(val, member)	((u32)(val) << SQ_CTRL_##member##_SHIFT)
 
@@ -32,20 +32,20 @@ int hinic_create_qps(void *hwdev, u16 qp_num, u16 sq_depth, u16 rq_depth,
 		     struct irq_info *rq_msix_arry, int max_sq_sge);
 void hinic_free_qps(void *hwdev);
 
-/* init qps ctxt and set sq ci attr and arm all sq*/
+/* init qps ctxt and set sq ci attr and arm all sq */
 int hinic_init_qp_ctxts(void *hwdev);
 void hinic_free_qp_ctxts(void *hwdev);
 
-/* function table and root context set*/
+/* function table and root context set */
 int hinic_set_parameters(void *hwdev, u8 *mac, u16 rx_buf_size, u32 mtu);
 void hinic_clear_parameters(void *hwdev);
 
-/* The function is internally invoked. set_arm_bit function*/
+/* The function is internally invoked. set_arm_bit function */
 int hinic_enable_tx_irq(void *hwdev, u16 q_id);
 
 int hinic_rx_tx_flush(void *hwdev);
 
-/* Obtain sq/rq number of idle wqebb*/
+/* Obtain sq/rq number of idle wqebb */
 int hinic_get_sq_free_wqebbs(void *hwdev, u16 q_id);
 int hinic_get_rq_free_wqebbs(void *hwdev, u16 q_id);
 
@@ -60,15 +60,15 @@ void *hinic_get_sq_wqe(void *hwdev, u16 q_id,
 void hinic_update_sq_pi(void *hwdev, u16 q_id, int num_wqebbs,
 			u16 *pi, u8 *owner);
 
-/* including cross-page process and press the doorbell 20170425*/
+/* including cross-page process and press the doorbell */
 void hinic_send_sq_wqe(void *hwdev, u16 q_id, void *wqe,
 		       int wqebb_cnt, int cos);
 
 void hinic_update_sq_local_ci(void *hwdev, u16 q_id, int wqebb_cnt);
 
-/* Refreshes the rq buff*/
+/* Refreshes the rq buff */
 void *hinic_get_rq_wqe(void *hwdev, u16 q_id, u16 *pi);
-/* gupdate rq pi, is the latest pi, function does not need to calculate*/
+/* gupdate rq pi, is the latest pi, function does not need to calculate */
 void hinic_return_rq_wqe(void *hwdev, u16 q_id, int num_wqebbs);
 
 void hinic_update_rq_delta(void *hwdev, u16 q_id, int num_wqebbs);
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_nictool.c b/drivers/net/ethernet/huawei/hinic/hinic_nictool.c
index 377ac67..9a2cb00 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_nictool.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_nictool.c
@@ -1364,7 +1364,7 @@ static int get_pf_dev_info(char *dev_name, struct msg_module *nt_msg)
 	chipif_get_all_pf_dev_info(dev_info, i,
 				   card_info->func_handle_array);
 
-	/* Copy the dev_info to user mode*/
+	/* Copy the dev_info to user mode */
 	if (copy_to_user(nt_msg->out_buf, dev_info, sizeof(dev_info))) {
 		pr_err("Copy dev_info to user fail\n");
 		return -EFAULT;
@@ -1446,7 +1446,7 @@ static int get_card_func_info(char *dev_name, struct msg_module *nt_msg)
 
 	card_func_info.usr_api_phy_addr = g_card_phy_addr[id];
 
-	/* Copy the dev_info to user mode*/
+	/* Copy the dev_info to user mode */
 	if (copy_to_user(nt_msg->out_buf, &card_func_info,
 			 sizeof(card_func_info))) {
 		pr_err("Copy dev_info to user fail\n");
@@ -2315,7 +2315,7 @@ int if_nictool_exist(void)
 
 /**
  * nictool_k_init - initialize the hw interface
- **/
+ */
 int nictool_k_init(void)
 {
 	int ret;
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_qe_def.h b/drivers/net/ethernet/huawei/hinic/hinic_qe_def.h
index a5b4e6f..db6e459 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_qe_def.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_qe_def.h
@@ -23,7 +23,7 @@
 #endif /* __cplusplus */
 
 #define HINIC_SQ_WQEBB_SIZE	64
-#define HINIC_RQ_WQE_SIZE		32
+#define HINIC_RQ_WQE_SIZE	32
 #define HINIC_SQ_WQEBB_SHIFT	6
 #define HINIC_RQ_WQEBB_SHIFT	5
 
@@ -43,14 +43,14 @@
 #define SQ_CTRL_BUFDESC_SECT_LEN_SHIFT			0
 #define SQ_CTRL_TASKSECT_LEN_SHIFT			16
 #define SQ_CTRL_DATA_FORMAT_SHIFT			22
-#define SQ_CTRL_LEN_SHIFT						29
-#define SQ_CTRL_OWNER_SHIFT					31
+#define SQ_CTRL_LEN_SHIFT				29
+#define SQ_CTRL_OWNER_SHIFT				31
 
-#define SQ_CTRL_BUFDESC_SECT_LEN_MASK		0xFFU
+#define SQ_CTRL_BUFDESC_SECT_LEN_MASK			0xFFU
 #define SQ_CTRL_TASKSECT_LEN_MASK			0x1FU
 #define SQ_CTRL_DATA_FORMAT_MASK			0x1U
-#define SQ_CTRL_LEN_MASK						0x3U
-#define SQ_CTRL_OWNER_MASK					0x1U
+#define SQ_CTRL_LEN_MASK				0x3U
+#define SQ_CTRL_OWNER_MASK				0x1U
 
 #define SQ_CTRL_GET(val, member)	(((val) >> SQ_CTRL_##member##_SHIFT) \
 					& SQ_CTRL_##member##_MASK)
@@ -59,21 +59,21 @@
 					(~(SQ_CTRL_##member##_MASK << \
 					SQ_CTRL_##member##_SHIFT)))
 
-#define SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT		2
+#define SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT			2
 #define SQ_CTRL_QUEUE_INFO_UFO_SHIFT			10
 #define SQ_CTRL_QUEUE_INFO_TSO_SHIFT			11
-#define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT	12
+#define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT		12
 #define SQ_CTRL_QUEUE_INFO_MSS_SHIFT			13
-#define SQ_CTRL_QUEUE_INFO_SCTP_SHIFT		27
+#define SQ_CTRL_QUEUE_INFO_SCTP_SHIFT			27
 #define SQ_CTRL_QUEUE_INFO_UC_SHIFT			28
 #define SQ_CTRL_QUEUE_INFO_PRI_SHIFT			29
 
-#define SQ_CTRL_QUEUE_INFO_PLDOFF_MASK		0xFFU
+#define SQ_CTRL_QUEUE_INFO_PLDOFF_MASK			0xFFU
 #define SQ_CTRL_QUEUE_INFO_UFO_MASK			0x1U
 #define SQ_CTRL_QUEUE_INFO_TSO_MASK			0x1U
-#define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK	0x1U
+#define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK		0x1U
 #define SQ_CTRL_QUEUE_INFO_MSS_MASK			0x3FFFU
-#define SQ_CTRL_QUEUE_INFO_SCTP_MASK		0x1U
+#define SQ_CTRL_QUEUE_INFO_SCTP_MASK			0x1U
 #define SQ_CTRL_QUEUE_INFO_UC_MASK			0x1U
 #define SQ_CTRL_QUEUE_INFO_PRI_MASK			0x7U
 
@@ -94,18 +94,18 @@
 #define	SQ_TASK_INFO0_INNER_L3TYPE_SHIFT	10
 #define	SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT	12
 #define	SQ_TASK_INFO0_PARSE_FLAG_SHIFT		13
-#define	SQ_TASK_INFO0_UFO_AVD_SHIFT			14
-#define	SQ_TASK_INFO0_TSO_UFO_SHIFT			15
-#define   SQ_TASK_INFO0_VLAN_TAG_SHIFT		16
+#define	SQ_TASK_INFO0_UFO_AVD_SHIFT		14
+#define	SQ_TASK_INFO0_TSO_UFO_SHIFT		15
+#define SQ_TASK_INFO0_VLAN_TAG_SHIFT		16
 
 #define	SQ_TASK_INFO0_L2HDR_LEN_MASK		0xFFU
 #define	SQ_TASK_INFO0_L4OFFLOAD_MASK		0x3U
 #define	SQ_TASK_INFO0_INNER_L3TYPE_MASK		0x3U
-#define	SQ_TASK_INFO0_VLAN_OFFLOAD_MASK	0x1U
+#define	SQ_TASK_INFO0_VLAN_OFFLOAD_MASK		0x1U
 #define	SQ_TASK_INFO0_PARSE_FLAG_MASK		0x1U
-#define	SQ_TASK_INFO0_UFO_AVD_MASK			0x1U
-#define   SQ_TASK_INFO0_TSO_UFO_MASK			0x1U
-#define   SQ_TASK_INFO0_VLAN_TAG_MASK			0xFFFFU
+#define	SQ_TASK_INFO0_UFO_AVD_MASK		0x1U
+#define SQ_TASK_INFO0_TSO_UFO_MASK		0x1U
+#define SQ_TASK_INFO0_VLAN_TAG_MASK		0xFFFFU
 
 #define SQ_TASK_INFO0_SET(val, member)			\
 		(((u32)(val) & SQ_TASK_INFO0_##member##_MASK) <<	\
@@ -114,11 +114,11 @@
 		(((val) >> SQ_TASK_INFO0_##member##_SHIFT) &	\
 		SQ_TASK_INFO0_##member##_MASK)
 
-#define	SQ_TASK_INFO1_MD_TYPE_SHIFT			8
+#define	SQ_TASK_INFO1_MD_TYPE_SHIFT		8
 #define SQ_TASK_INFO1_INNER_L4LEN_SHIFT		16
 #define SQ_TASK_INFO1_INNER_L3LEN_SHIFT		24
 
-#define	SQ_TASK_INFO1_MD_TYPE_MASK			0xFFU
+#define	SQ_TASK_INFO1_MD_TYPE_MASK		0xFFU
 #define SQ_TASK_INFO1_INNER_L4LEN_MASK		0xFFU
 #define SQ_TASK_INFO1_INNER_L3LEN_MASK		0xFFU
 
@@ -129,10 +129,10 @@
 		(((val) >> SQ_TASK_INFO1_##member##_SHIFT) &	\
 		SQ_TASK_INFO1_##member##_MASK)
 
-#define SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT		0
+#define SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT	0
 #define SQ_TASK_INFO2_OUTER_L3LEN_SHIFT		8
 #define SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT	16
-#define SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT		24
+#define SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT	24
 
 #define SQ_TASK_INFO2_TUNNEL_L4LEN_MASK		0xFFU
 #define SQ_TASK_INFO2_OUTER_L3LEN_MASK		0xFFU
@@ -158,7 +158,7 @@
 #define SQ_DB_OFF						0x00000800
 #define SQ_DB_INFO_HI_PI_SHIFT					0
 #define SQ_DB_INFO_QID_SHIFT					8
-#define SQ_DB_INFO_CFLAG_SHIFT				23
+#define SQ_DB_INFO_CFLAG_SHIFT					23
 #define SQ_DB_INFO_COS_SHIFT					24
 #define SQ_DB_INFO_TYPE_SHIFT					27
 #define SQ_DB_INFO_HI_PI_MASK					0xFFU
@@ -170,25 +170,25 @@
 					SQ_DB_INFO_##member##_MASK) << \
 					SQ_DB_INFO_##member##_SHIFT)
 
-#define SQ_DB_PI_LOW_MASK		0xFF
-#define SQ_DB_PI_LOW(pi)		((pi) & SQ_DB_PI_LOW_MASK)
-#define SQ_DB_PI_HI_SHIFT		8
-#define SQ_DB_PI_HIGH(pi)		((pi) >> SQ_DB_PI_HI_SHIFT)
+#define SQ_DB_PI_LOW_MASK			0xFF
+#define SQ_DB_PI_LOW(pi)			((pi) & SQ_DB_PI_LOW_MASK)
+#define SQ_DB_PI_HI_SHIFT			8
+#define SQ_DB_PI_HIGH(pi)			((pi) >> SQ_DB_PI_HI_SHIFT)
 #define SQ_DB_ADDR(sq, pi)		((u64 *)((sq)->db_addr + SQ_DB_OFF) + \
 					SQ_DB_PI_LOW(pi))
-#define SQ_DB				1
-#define SQ_CFLAG_DP			0	/* CFLAG_DATA_PATH */
+#define SQ_DB					1
+#define SQ_CFLAG_DP				0	/* CFLAG_DATA_PATH */
 
 /*********************** RQ_CTRL ******************/
 #define	RQ_CTRL_BUFDESC_SECT_LEN_SHIFT		0
 #define	RQ_CTRL_COMPLETE_FORMAT_SHIFT		15
-#define RQ_CTRL_COMPLETE_LEN_SHIFT			27
-#define RQ_CTRL_LEN_SHIFT						29
+#define RQ_CTRL_COMPLETE_LEN_SHIFT		27
+#define RQ_CTRL_LEN_SHIFT			29
 
 #define	RQ_CTRL_BUFDESC_SECT_LEN_MASK		0xFFU
 #define	RQ_CTRL_COMPLETE_FORMAT_MASK		0x1U
-#define RQ_CTRL_COMPLETE_LEN_MASK			0x3U
-#define RQ_CTRL_LEN_MASK						0x3U
+#define RQ_CTRL_COMPLETE_LEN_MASK		0x3U
+#define RQ_CTRL_LEN_MASK			0x3U
 
 #define RQ_CTRL_SET(val, member)			(((val) & \
 					RQ_CTRL_##member##_MASK) << \
@@ -203,7 +203,7 @@
 					RQ_CTRL_##member##_SHIFT)))
 
 #define RQ_CQE_STATUS_CSUM_ERR_SHIFT		0
-#define RQ_CQE_STATUS_NUM_LRO_SHIFT			16
+#define RQ_CQE_STATUS_NUM_LRO_SHIFT		16
 #define RQ_CQE_STATUS_LRO_PUSH_SHIFT		25
 #define RQ_CQE_STATUS_LRO_ENTER_SHIFT		26
 #define RQ_CQE_STATUS_LRO_INTR_SHIFT		27
@@ -213,7 +213,7 @@
 #define RQ_CQE_STATUS_FLUSH_SHIFT		28
 
 #define RQ_CQE_STATUS_CSUM_ERR_MASK		0xFFFFU
-#define RQ_CQE_STATUS_NUM_LRO_MASK			0xFFU
+#define RQ_CQE_STATUS_NUM_LRO_MASK		0xFFU
 #define RQ_CQE_STATUS_LRO_PUSH_MASK		0X1U
 #define RQ_CQE_STATUS_LRO_ENTER_MASK		0X1U
 #define RQ_CQE_STATUS_LRO_INTR_MASK		0X1U
@@ -290,7 +290,7 @@
 
 #define SECT_SIZE_BYTES(size)	((size) << 3)
 
-#define HINIC_PF_SET_VF_ALREADY						0x4
+#define HINIC_PF_SET_VF_ALREADY					0x4
 #define HINIC_MGMT_STATUS_EXIST					0x6
 
 #define WQS_BLOCKS_PER_PAGE		4
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_rx.h b/drivers/net/ethernet/huawei/hinic/hinic_rx.h
index 89be4b6..9b4abfe 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_rx.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_rx.h
@@ -16,7 +16,7 @@
 #ifndef HINIC_RX_H
 #define HINIC_RX_H
 
-/*rx cqe checksum err*/
+/* rx cqe checksum err */
 #define HINIC_RX_CSUM_IP_CSUM_ERR	BIT(0)
 #define HINIC_RX_CSUM_TCP_CSUM_ERR	BIT(1)
 #define HINIC_RX_CSUM_UDP_CSUM_ERR	BIT(2)
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_sriov.c b/drivers/net/ethernet/huawei/hinic/hinic_sriov.c
index 172f650..0ec12d9 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_sriov.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_sriov.c
@@ -378,7 +378,7 @@ int hinic_ndo_get_vf_config(struct net_device *netdev,
  * @link: required link state
  * Return: 0 - success, negative - failure
  * Set the link state of a specified VF, regardless of physical link state
- **/
+ */
 int hinic_ndo_set_vf_link_state(struct net_device *netdev, int vf_id, int link)
 {
 	struct hinic_nic_dev *adapter = netdev_priv(netdev);
-- 
1.8.3.1

