From 038fa802df45a1a8727c721916b0b8e7039d9d2d Mon Sep 17 00:00:00 2001 From: Xie XiuQi Date: Tue, 29 Jan 2019 17:38:32 +0800 Subject: [PATCH 2827/2944] openEuler: arm64/mpam: add mpam extension runtime detection commit 5782085949ef5d1ddb5a2de63d5195297b3b48b5 openEuler-1.0 hulk inclusion category: feature bugzilla: 5510 CVE: NA According to <> document, we add MPAM extension feature runtime detection. Signed-off-by: Xie XiuQi Reviewed-by: Hanjun Guo Signed-off-by: Yang Yingliang Signed-off-by: Xin Hao Reviewed-by: Baolin Wang --- arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/kernel/cpufeature.c | 13 +++++++++++++ arch/arm64/kernel/mpam.c | 3 +++ 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index f2591bc..698b7ae 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -57,6 +57,7 @@ #define ARM64_WORKAROUND_1418040 36 #define ARM64_WORKAROUND_1542419 37 #define ARM64_HAS_IRQ_PRIO_MASKING 38 -#define ARM64_NCAPS 39 +#define ARM64_HAS_MPAM 39 +#define ARM64_NCAPS 40 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9d9461f..e63df34 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -528,6 +528,7 @@ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 #define ID_AA64PFR0_DIT_SHIFT 48 +#define ID_AA64PFR0_MPAM_SHIFT 40 #define ID_AA64PFR0_SVE_SHIFT 32 #define ID_AA64PFR0_RAS_SHIFT 28 #define ID_AA64PFR0_GIC_SHIFT 24 @@ -538,6 +539,7 @@ #define ID_AA64PFR0_EL1_SHIFT 4 #define ID_AA64PFR0_EL0_SHIFT 0 +#define ID_AA64PFR0_MPAM 0x1 #define ID_AA64PFR0_SVE 0x1 #define ID_AA64PFR0_RAS_V1 0x1 #define ID_AA64PFR0_FP_NI 0xf diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index ee4b99d..d46a318 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -154,6 +154,7 @@ static int __init register_cpu_hwcaps_dumper(void) static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), @@ -1331,6 +1332,18 @@ static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, .cpu_enable = cpu_clear_disr, }, #endif /* CONFIG_ARM64_RAS_EXTN */ +#ifdef CONFIG_MPAM + { + .desc = "ARM64 MPAM Extension Support", + .capability = ARM64_HAS_MPAM, + .type = ARM64_CPUCAP_SCOPE_SYSTEM, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64PFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64PFR0_MPAM_SHIFT, + .min_field_value = ID_AA64PFR0_MPAM, + }, +#endif /* CONFIG_MPAM */ { .desc = "Data cache clean to the PoU not required for I/D coherence", .capability = ARM64_HAS_CACHE_IDC, diff --git a/arch/arm64/kernel/mpam.c b/arch/arm64/kernel/mpam.c index 542fd7f..b83fd58 100644 --- a/arch/arm64/kernel/mpam.c +++ b/arch/arm64/kernel/mpam.c @@ -406,6 +406,9 @@ static __init bool get_rdt_mon_resources(void) static __init bool get_resctrl_resources(void) { + if (!cpus_have_const_cap(ARM64_HAS_MPAM)) + return false; + rdt_alloc_capable = get_rdt_alloc_resources(); rdt_mon_capable = get_rdt_mon_resources(); -- 1.8.3.1